1. Field of the Invention
The present invention relates to a read only semiconductor memory device, and particularly to a construction and method for repairing a defective bit in a mask ROM (read only memory).
2. Description of the Related Art
Semiconductor memory devices include read only memory devices, e.g., ROM memory (referred to simply as ROM hereinafter) for storing fixed data. Such a ROM has a bit formed of one transistor to provide a suitable construction for high integration and reduced cost per bit. Therefore, ROMs have been widely used in various applications.
Generally, for effective utilization of the ROM, valid data are written over a full memory space (address space) thereof. In some applications, however, the memory space of the ROM is partially maintained in an unused (or undefined) state.
The storage capacity of a ROM is mainly determined by the number of address bits and the number of bits of read out data. For example, if an address comprises 20 bits and read out data comprises 8 bits, the storage capacity of such a ROM is 8 mega bits=2.sup.20 .times.8 (=1 M bytes). The ROM is used for storing an application specific program or data. If the program or data requires 640 K bits, a ROM with 1 M bit storage capacity is used because available ROM's storage capacity is predetermined, as 256 K bits, 512 K bits, 1 M bit and so on. In this case, the remaining address region (360 K bits in the above example) is maintained in the unused state or undefined state. In general, data of a predetermined fixed logic level is written into the memory cells in the remaining unused address region. As an example, a Kanji-character generator in accordance with the Japanese Industrial Standard will now be considered.
FIG. 14 shows a mapping of a memory space of a ROM used in such a Kanji-character generator. In FIG. 14, a memory space 100 of the ROM includes regions 101 and 103 for having valid data written therein where a Kanji character code is allotted and a Kanji character is defined, and an undefined region 102 where a Kanji character is not defined while a character code is allocated, and an unused region 104 where a character code as well as Kanji characters are not defined. In code assignment of Kanji characters in accordance with the Japanese Industrial Standard, one Kanji character is defined by a first byte (area) indicating an X-address and a second byte (point) indicating a Y-address. In the Kanji character code assignment, the first type comprises 7 bits and the second byte comprises 7 bits, so that 2.sup.14 (=16384) Kanji characters can be defined. However, only 7144 Kanji characters are defined in the Japanese Industrial Standard. The remaining 9240 Kanji characters are not defined, and the region 102 is maintained in the undefined state. If the employed ROM has the storage capacity of 2.sup.16 bytes (=64 K bytes) when one Kanji-character requires one byte, 12 K (2.sup.16 -2.sup.14) addresses or 12 K byte memory cells are used to produce the unused region 104. In this assignment, the 8th to 15th areas are in the undefined state.
In a mask ROM, data is written in a manufacturing process. Therefore, data of predetermined logic, i.e., logic "0" or "1" is written in the undefined region (or unused region) in such a mask ROM. A manufacturer can use the undefined region 102 to define desired additional Kanji characters as necessary.
For economical reasons, a mask ROM has been proposed that includes a redundant circuit for outputting data of a predetermined logical level of logic "0" or "1" when an address of region 102 is designated, in order to construct the ROM having the mapping shown in FIG. 14 and the ROM having valid data written in the undefined region 102 in the same chip. An example of such ROMs has been disclosed in the Japanese Examined Patent Publication No. 63-53639 (Unexamined Patent Publication No. 60-95793) and Japanese Examined Patent Publication No. 64-5397 (Unexamined Patent Publication No. 60-115098).
FIG. 15 schematically shows a whole construction of a conventional mask ROM. In FIG. 15, the mask ROM includes a memory array 5 having a plurality of memory cells arranged in a matrix of rows and columns, an address buffer 1 for performing waveform shaping and amplification of an address signal applied to an address input terminal 10 to generate an internal address signal, an X-decoder 2 which decodes an internal row address signal supplied from address buffer 1 to select a row in memory array 5, a Y-decoder 3 which decodes an internal column address signal supplied from address buffer 1 to generate a signal for selecting a column in memory array 5, and a Y-gate 4 which responds to a column selecting signal supplied from Y-decoder 3 to connect a corresponding column in memory array 5 to a sense amplifier 6. An address signal applied to address input terminal 10 includes address bits A0-An. In the ROM, generally, bits of data from a word is read from memory array 5. Therefore, the column selecting signal supplied from Y-decoder 3 designates a plurality of columns in memory array 5. Sense amplifier 6 detects and amplifies the data of the memory cells selected by Y-gate 4.
The ROM further includes an address coincidence detecting circuit 9 which receives an internal address signal from address buffer 1 to determine whether or not the internal address signal designates an address in a specific region in memory array 5, and an output circuit 7 which is responsive to a coincidence detection signal from address coincidence detecting circuit 9 to select, as data to be transmitted to data output terminal 11, one of memory cell data supplied from sense amplifier 6 and data of a predetermined logical level. Coincidence detecting circuit 9 stores in advance an address signal (region address signal) indicative of the specific region in memory array 5, and detects coincidence/noncoincidence of the region address signal and an internal address signal from address buffer 1. Output circuit 7 includes a predetermined level fixing circuit (not shown), which is activated upon generation of the coincidence detection signal from address coincidence detecting circuit 9 to set the potential level of output terminal 11 at a predetermined potential.
The ROM further includes a control circuit 8 which receives an externally applied chip enable signal /CE and an output enable signal /OE to generate various kinds of internal control signals. Generally, address buffer 1 is formed of a static circuit, and generates an internal address signal as externally applied address signal bits A0-An are received. Control circuit 8 generates an internal control signal for determining an activation timing of sense amplifier 6 and a data output timing of output circuit 7. The activation timing of sense amplifier 6 is determined by chip enable signal /CE. The data output timing of output circuit 7 is determined by output enable signal /OE. An operation will be described below.
Address coincidence detecting circuit 9 has been programmed to store the region address signal indicative of the specific memory region (i.e., address region) in memory array 5. Address buffer 1 generates an internal address signal based on external address signal bits A0-An applied to address input terminal 10. The internal address signal includes an internal row address signal and an internal column address signal.
X-decoder 2 decodes the internal row address signal from address buffer 1 to select a corresponding row in memory array 5. The memory cells connected to the selected row in the memory array 5 are connected to the corresponding columns. While X-decoder 2 is carrying out the row selecting operation, Y-decoder 3 decodes the internal column address signal from address buffer 1 to generate the column selecting signal. Y-gate 4 responds to the column selecting signal to connect a corresponding column in memory array 5 to sense amplifier 6.
In memory array 5, the potential of each column has changed in accordance with the data stored in each related memory cell, when Y-gate 4 performs the column selecting operation. Sense amplifier 6 detects and amplifies the signal potential on the column selected by Y-gate 4. Data of the memory cells detected and amplified by sense amplifier 6 is transmitted to output circuit 7.
When address signal bits A0-An designate an address in the address region stored in address coincidence detecting circuit 9, address coincidence detecting circuit 9 generates the coincidence detecting signal. When the address coincidence detecting signal is generated, output circuit 7 activates the predetermined level fixing circuit included therein, ignores the data of the memory cells transmitted from sense amplifier 6, and sets the potential level of data output terminal 11 at the predetermined level of the logic "1" or "0". In this operation, output data D0-Dm is "1 . . . 1", or "0 . . . 0".
When address coincidence detecting circuit 9 does not generate the coincidence detecting signal, output circuit 7 sets the predetermined level fixing circuit included therein at the inactive state, and transmits the memory cell data received from sense amplifier 6 to data output terminal 11.
According to the above construction, all the data stored in the memory space (or address region) designated by address coincidence detecting circuit 9 can be forcedly changed to the logic "1" or "0".
In the construction of the ROM shown in FIG. 15, an arbitrary region in the memory space made by memory array 5 can be changed into the region which stores only the data of the logic "0" or "1". An arrangement in which the above construction is applied to a redundant circuit for repairing a defective bit in a mask ROM is disclosed by Hotta et al. in the article titled "HIGH DENSITY MASK ROM MEMORY CELL WITH A BANK SELECTION ARCHITECTURE AND A NEW REDUNDANCY SCHEME FOR MASK ROM", Institute of Electronics, Informations, Communications and Electrics Engineers, Technology Research Report, Vol. 88 No. 125, July 1988, pp. 13-18.
In the Hotta et al. reference, when an address of the memory region in which every data provides "0" or "1" is designated, the data read out of the memory cell is rendered invalid, and previously programmed data of "0" or "1" is alternatively output. According to this redundant circuit construction, a defective bit in the memory region stored in the address coincidence detecting circuit can be effectively repaired because ten defective bit data is replaced by the predetermined fixed data of logic "1" or "0". The repairing of defective bits improves the product yield because a ROM having defective bits can be marketed as a reliable product instead of being disposed. The product yield means the rate of accepted or non-defective product to all the products. Even an unused region is required to include no defective bits for a reliable product. The Hotta et al. reference states that, if data in the region including successively data of only "0s" or only "1s" over 2 K bytes or more is replaced with the previously programmed data, using this circuit, it can be expected that a product yield is improved by approximately 5% in 16 M bit mask ROM.
The Hotta et al. reference also discloses that, as the storage capacity of a mask ROM increases, the storage region of the data of only "0s" or only "1s" tends to increase, and such data continuity region becomes approximately 100 K bytes in the 16 M-bit mask ROM.
The construction of the mask ROM described above can easily achieve the replacement of the data in the continuity region 102 shown in FIG. 14 with the data of "0s" or "1s".
However, as shown in FIG. 16, if a region 152 which stores only the data of all "1s" is divided by a region 154 which stores only the opposite logic data, i.e., data of all "0s", the data cannot be replaced effectively. This is true also in a case where region 152 has stored only the data of all "0s" and region 154 has stored only the data of all "0s".
Further, effective data replacement cannot be performed in a case where, as shown in FIG. 17, a memory space 160 contains valid regions (i.e., regions for storing valid data) 162, 166 and 168, and an unused region 164 contains the valid regions 166 and 168. In the construction having a mapping shown in FIG. 17, it is necessary to divide unused region 164 into five regions A, B, C, D and E, and to detect the coincidence of the addresses for the respective regions. Therefore, efficient data replacement cannot be carried out by a simple circuit construction.
Generally, the output data of the mask ROM includes a plurality of bits. In this case, if address regions including the successions of "0" or "1" are respectively related to the different data output pin terminals, i.e., different memory blocks, the above described redundant construction cannot effectively carry out the data replacement. If the mask ROM has a data width of 16 bits, 16 bit data and 8 bit data may be stored therein. If 8 bit data is required, the address regions forming invalid regions are different in the respective memory blocks. Also in this case, the above described redundant construction of the prior art cannot perform effective data replacement.
In the conventional redundant construction of the mask ROM, the predetermined data is replaced only to the regions including only the data having all "0" or "1". Therefore, the replacement of the data cannot be performed flexibly in accordance with the memory regions of the data, and thus the product yield cannot be improved to a large extent.